Unless stated otherwise, each instruction increments the program counter by 4. We use $$\sext(b)$$ to denote a sign extension of a bit string to 32 bit and $$\zext(b)$$ for a zero extension of a bit string to 32 bit (see Sign and Zero Extension). Note that instructions using an immediate perform either sign or zero extension of the 16-bit immediate to 32 bit depending on the opcode. $$\blts$$ und $$\bltu$$ denote signed and unsigned comparisons. $$W[a]\text{,}$$ $$H[a]$$ und $$B[a]$$ denote memory contents at address $$a$$ in form of a word, half word or byte.
We use the following abbreviation to compute the new $$pc$$ address for a conditional jump:
 Mnem Args Semantics Comment addu $$\rd\ \rs\ \rt$$ $$\rd\gets\rs+\rt$$ Add two regs addiu $$\rd\ \rs\ i$$ $$\rd\gets\rs+\sei$$ Add reg with immediate subu $$\rd\ \rs\ \rt$$ $$\rd\gets\rs-\rt$$ Subtract two regs mul $$\rd\ \rs\ \rt$$ $$\rd\gets\rs\cdot\rt$$ Multiply two reg div $$\rd\ \rs\ \rt$$ $$\rd\gets\rs\mathop{/}\rt$$ Divide two regs rem $$\rd\ \rs\ \rt$$ $$\rd\gets\rs\mathop{\%}\rt$$ Remainder of division and $$\rd\ \rs\ \rt$$ $$\rd\gets\rs\band\rt$$ Bitwise and and $$\rd\ \rs\ i$$ $$\rd\gets\rs\band\zei$$ Bitwise and with immediate or $$\rd\ \rs\ \rt$$ $$\rd\gets\rs\bor\rt$$ Bitwise or ori $$\rd\ \rs\ i$$ $$\rd\gets\rs\bor\zei$$ Bitwise or with immediate xor $$\rd\ \rs\ \rt$$ $$\rd\gets\rs\bxor\rt$$ Bitwise xor xori $$\rd\ \rs\ i$$ $$\rd\gets\rs\bxor\zei$$ Bitwise xor with immediate nor $$\rd\ \rs\ \rt$$ $$\rd\gets\bneg{\rs\bor\rt}$$ Complement of or lui $$\rd\ \ i$$ $$\rd\gets i_{15}\dots i_{0}\bconcat 0^{16}$$ Load upper half-word of reg sll $$\rd\ \rs\ n$$ $$\rd\gets \rs_{31-n}\dots\rs_0\bconcat 0^n$$ Shift left by $$n$$ srl $$\rd\ \rs\ n$$ $$\rd\gets 0^n\bconcat\rs_{31}\dots\rs_{n}$$ Unsigned shift right by $$n$$ sra $$\rd\ \rs\ n$$ $$\rd\gets (\rs_{31})^n\bconcat\rs_{31}\dots\rs_{n}$$ Signed shift right by $$n$$ sllv $$\rd\ \rs\ \rt$$ $$\rd\gets \rs_{31-n}\dots\rs_0\bconcat 0^n$$ $$n\defeq\rt$$ srlv $$\rd\ \rs\ \rt$$ $$\rd\gets 0^n\bconcat\rs_{31}\dots\rs_{n}$$ $$n\defeq\rt$$ srav $$\rd\ \rs\ \rt$$ $$\rd\gets (\rs_{31})^n\bconcat\rs_{31}\dots\rs_{n}$$ $$n\defeq\rt$$ slt $$\rd\ \rs\ \rt$$ $$\rd\gets\ite{\rs\blts\rt}10$$ Signed comparison of two regs sltu $$\rd\ \rs\ \rt$$ $$\rd\gets\ite{\rs\bltu\rt}10$$ Unsigned comparison of two regs slti $$\rd\ \rs\ i$$ $$\rd\gets\ite{\rs\blts\sei}10$$ Signed comparison of reg with imm. sltiu $$\rd\ \rs\ i$$ $$\rd\gets\ite{\rs\bltu\sei}10$$ Unsigned comparison of reg with imm. lw $$\rd\ i(\rs)$$ $$\rd\gets W[\rs+\sei]$$ Load word lh $$\rd\ i(\rs)$$ $$\rd\gets\sext(H[\rs\badd\sei])$$ Load half word with sign extension lb $$\rd\ i(\rs)$$ $$\rd\gets\sext(B[\rs\badd\sei])$$ Load byte with sign extension lhu $$\rd\ i(\rs)$$ $$\rd\gets\zext(H[\rs\badd\sei])$$ Load half word with zero extension lbu $$\rd\ i(\rs)$$ $$\rd\gets\zext(B[\rs\badd\sei])$$ Load byte with zero extension sw $$\rd\ i(\rs)$$ $$W[\rs\badd\sei]\gets\rd$$ Store word sh $$\rd\ i(\rs)$$ $$H[\rs\badd\sei]\gets\rd\bft{15}0$$ Store half word sb $$\rd\ i(\rs)$$ $$B[\rs\badd\sei]\gets\rd\bft70$$ Store byte beq $$\rs\ \rt\ \offset$$ $$\pc\gets\cbranch(\rs=\rt)$$ bne $$\rs\ \rt\ \offset$$ $$\pc\gets\cbranch(\rs\ne\rt)$$ b$$cc$$z $$\rt\ \offset$$ $$\pc\gets\cbranch(\rt\mathop{cc} 0)$$ $$cc\in\{\text{lt},\text{gt},\text{le},\text{ge}\}$$ (signed comparison) jal $$\addr$$ $$\ra\gets\pc\badd 4, \pc\gets\addr$$ Function call jr $$\rs$$ $$\pc\gets\rs$$ Indirect jump syscall   Invoke operating system li $$\rd\ i$$ $$\rd\gets i$$ Load constant into reg la $$\rd\ l$$ $$\rd\gets \addr$$ Load address of label into reg move $$\rd\ \rs$$ $$\rd\gets\rs$$ Copy reg not $$\rd\ \rs$$ $$\rd\gets\bneg{\rs}$$ Bitwise complement neg $$\rd\ \rs$$ $$\rd\gets-\rs$$ $$\cdot(-1)$$ b $$\offset$$ $$\pc\gets\pc\badd 4\cdot(1\badd \sei)$$ Unconditional jump b$$cc$$ $$\rs\ \rt\ \offset$$ $$\pc\gets\cbranch(\mathit{cc})$$ $$cc\in\{\text{lt},\text{gt},\text{le},\text{ge}\}$$ (signed comparison)