Section A.1 Instruction Set Reference
Here, we summarize the RV32I instructions of the RISC-V ISA and OS calls that are most important for this book. The official RISC-V reference [3] provides further details on the RV32I instruction set.
Unless stated otherwise, each instruction increments the program counter by 4. We use \(\sext(b)\) to denote a sign extension of a bit string to 32 bit and \(\zext(b)\) for a zero extension of a bit string to 32 bit (see Sign and Zero Extension). Note that instructions using an immediate perform either sign or zero extension of the 16-bit immediate to 32 bit depending on the opcode. \(\blts\) und \(\bltu\) denote signed and unsigned comparisons. \(W[a]\text{,}\) \(H[a]\) und \(B[a]\) denote memory contents at address \(a\) in form of a word, half word or byte.
We use the following abbreviation to compute the new \(pc\) address for a conditional jump:
\begin{equation*}
\cbranch(cc)\defeq\pc\badd 4\cdot (1\badd\ite{cc}{\sext(i)}{0})
\end{equation*}
| Mnem | Args | Semantics | Comment |
| add | \(\rd\ \rs\ \rt \) | \(\rd\gets\rs+\rt \) | Add two regs |
| addi | \(\rd\ \rs\ i \) | \(\rd\gets\rs+\sei \) | Add reg with immediate |
| sub | \(\rd\ \rs\ \rt \) | \(\rd\gets\rs-\rt \) | Subtract two regs |
| mul | \(\rd\ \rs\ \rt \) | \(\rd\gets\rs\cdot\rt \) | Multiply two reg |
| div | \(\rd\ \rs\ \rt \) | \(\rd\gets\rs\mathop{/}\rt \) | Divide two regs |
| rem | \(\rd\ \rs\ \rt \) | \(\rd\gets\rs\mathop{\%}\rt \) | Remainder of division |
| and | \(\rd\ \rs\ \rt \) | \(\rd\gets\rs\band\rt \) | Bitwise and |
| andi | \(\rd\ \rs\ i \) | \(\rd\gets\rs\band\zei \) | Bitwise and with immediate |
| or | \(\rd\ \rs\ \rt \) | \(\rd\gets\rs\bor\rt \) | Bitwise or |
| ori | \(\rd\ \rs\ i \) | \(\rd\gets\rs\bor\zei \) | Bitwise or with immediate |
| xor | \(\rd\ \rs\ \rt \) | \(\rd\gets\rs\bxor\rt \) | Bitwise xor |
| xori | \(\rd\ \rs\ i \) | \(\rd\gets\rs\bxor\zei \) | Bitwise xor with immediate |
| auipc | \(\rd\ i \) | \(\rd\gets \pc + i_{31}\dots i_{12}\bconcat 0^{12} \) | Add upper immediate to pc |
| lui | \(\rd\ \ i \) | \(\rd\gets i_{19}\dots i_{0}\bconcat 0^{12} \) | Load unsigned immediate |
| slli | \(\rd\ \rs\ n \) | \(\rd\gets \rs_{31-n}\dots\rs_0\bconcat 0^n \) | Shift left by \(n\) |
| srli | \(\rd\ \rs\ n \) | \(\rd\gets 0^n\bconcat\rs_{31}\dots\rs_{n} \) | Unsigned shift right by \(n\) |
| srai | \(\rd\ \rs\ n \) | \(\rd\gets (\rs_{31})^n\bconcat\rs_{31}\dots\rs_{n} \) | Signed shift right by \(n\) |
| sll | \(\rd\ \rs\ \rt \) | \(\rd\gets \rs_{31-n}\dots\rs_0\bconcat 0^n \) | Shift left by \(n=\rt\) |
| srl | \(\rd\ \rs\ \rt \) | \(\rd\gets 0^n\bconcat\rs_{31}\dots\rs_{n} \) | Unsigned shift right by \(n=\rt\) |
| sra | \(\rd\ \rs\ \rt \) | \(\rd\gets (\rs_{31})^n\bconcat\rs_{31}\dots\rs_{n} \) | Signed shift right by \(n=\rt\) |
| slt | \(\rd\ \rs\ \rt \) | \(\rd\gets\ite{\rs\blts\rt}10 \) | Signed comparison of two regs |
| sltu | \(\rd\ \rs\ \rt \) | \(\rd\gets\ite{\rs\bltu\rt}10 \) | Unsigned comparison of two regs |
| slti | \(\rd\ \rs\ i \) | \(\rd\gets\ite{\rs\blts\sei}10 \) | Signed comparison of reg with imm. |
| sltiu | \(\rd\ \rs\ i \) | \(\rd\gets\ite{\rs\bltu\sei}10 \) | Unsigned comparison of reg with imm. |
| lw | \(\rd\ i(\rs) \) | \(\rd\gets W[\rs+\sei] \) | Load word |
| lh | \(\rd\ i(\rs) \) | \(\rd\gets\sext(H[\rs\badd\sei]) \) | Load half word with sign extension |
| lb | \(\rd\ i(\rs) \) | \(\rd\gets\sext(B[\rs\badd\sei]) \) | Load byte with sign extension |
| lhu | \(\rd\ i(\rs) \) | \(\rd\gets\zext(H[\rs\badd\sei]) \) | Load half word with zero extension |
| lbu | \(\rd\ i(\rs) \) | \(\rd\gets\zext(B[\rs\badd\sei]) \) | Load byte with zero extension |
| sw | \(\rd\ i(\rs) \) | \(W[\rs\badd\sei]\gets\rd \) | Store word |
| sh | \(\rd\ i(\rs) \) | \(H[\rs\badd\sei]\gets\rd_{15}\dots\rd_0 \) | Store half word |
| sb | \(\rd\ i(\rs) \) | \(B[\rs\badd\sei]\gets\rd_{7}\dots\rd_0 \) | Store byte |
| beq | \(\rs\ \rt\ \offset \) | \(\pc\gets\cbranch(\rs=\rt) \) | |
| bne | \(\rs\ \rt\ \offset \) | \(\pc\gets\cbranch(\rs\ne\rt) \) | |
| blt | \(\rs\ \rt\ \offset \) | \(\pc\gets\cbranch(\rs\blts\rs)\) | (signed comparison) |
| bge | \(\rs\ \rt\ \offset \) | \(\pc\gets\cbranch(\rs\bges\rs) \) | (signed comparison) |
| bltu | \(\rs\ \rt\ \offset \) | \(\pc\gets\cbranch(\rs\bltu\rs)\) | (unsigned comparison) |
| bgeu | \(\rs \rt \offset \) | \(\pc\gets\cbranch(\rs\bgeu\rs) \) | (unsigned comparison) |
| jal | \(\rd\ \offset \) | \(\rd\gets\pc+4, \pc\gets\pc+\offset \) | jump and link |
| jalr | \(\rd\ rs\ \offset \) | \(\rd\gets\pc+4, \pc\gets\rs+\offset \) | jump and link indirect |
| ecall | \(\) | \(\) | Invoke operating system |
| nop | \(\) | addi x0 x0 0 | Load constant into reg |
| li | \(\rd\ i \) | \(\rd\gets i \) | Load constant into reg |
| mv | \(\rd\ \rs \) | addi \(\rd\ \rs\ 0 \) | Copy reg |
| not | \(\rd\ \rs \) | xori \(\rd\ \rs\ -1 \) | Bitwise complement |
| neg | \(\rd\ \rs \) | sub \(\rd\ \text{x0}\ \rs \) | \(\rd=-\rs\) |
| bgt | \(\rs\ \rt\ \offset \) | blt \(\rt\ \rs \offset \) | Branch if greater (signed) |
| bgtu | \(\rs\ \rt\ \offset \) | bltu \(\rt\ \rs \offset \) | Branch if greater (unsigned) |
| ble | \(\rs\ \rt\ \offset \) | bge \(\rt\ \rs \offset \) | Branch if greater (signed) |
| bleu | \(\rs\ \rt\ \offset \) | bgeu \(\rt\ \rs \offset \) | Branch if greater (unsigned) |
| b\(cc\)z | \(\rs\ \offset \) | b\(cc\) \(\rs\ \text{x0}\ \offset \) | Branch with compare to zero |
| j | \(\offset \) | jal x0, \(\offset \) | unconditional jump |
| jr | \(\rs \) | jalr x0, 0(\(\rs\)) | indirect jump |
| call | \(\offset \) | jal x1, \(\offset \) | call subroutine |
| ret | \(\rs \) | jalr x0, 0(x1) | return from subroutine |
